Micron's 9650 SSD just hit 28 GB/s sequential reads. That's the headline from FMS 2026, where the chipmaker and Microchip Technology unveiled the industry's first production-grade PCIe Gen 6 storage stack built end-to-end for the AI era. The demonstration wasn't just a bench run, though. They showed it working together, which matters more than it sounds.
Why Gen 6 changes the math
PCIe Gen 5 maxes out at 32 GT/s per lane. Gen 6 doubles that to 64 GT/s, and Micron's new SSD proves the interface can actually deliver on that promise. The real bottleneck, though, has never been the drives themselves. It's been the plumbing. Plug a Gen 6 SSD into a Gen 5 switch and you're leaving half the speed on the table. Microchip's Switchtec Gen 6, built on 3nm and supporting 160 lanes, changes that. The two companies tested the pairing together and confirmed both sides run at full throughput without compromise.
The integration risk nobody talks about
Data center operators buying new hardware usually face a choice: either trust the vendor's word that components will play nicely together, or spend months validating the stack themselves. Microchip and Micron just handed them a shortcut. By jointly certifying their Gen 6 ecosystem, they've eliminated the guesswork. The Switchtec switches include hardware root of trust, multicast support, and CNSA 2.0 post-quantum cryptography, which matters for infrastructure that'll be running for the next decade.
What this means for the chip race
Micron being first to mass production in a new PCIe generation is a meaningful advantage, at least for the next 18 months. Design wins in data centers move slowly, but they stick around. AI infrastructure operators who integrate the 9650 into their builds today lock in compatibility and performance for years. Microchip gets the same benefit on the switching side, especially as cloud providers build out next-generation clusters designed from the ground up for language models and training workloads that actually demand this kind of throughput. Larry Hart from Micron tied the announcement directly to AI hardware demands, noting that storage performance needs to keep pace with what increasingly complex models require at the silicon level.
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